Chapter #7: Sequential Logic Case Studies

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Chapter #7: Sequential Logic Case Studies. Motivation. Flipflops: most primitive "packaged" sequential circuits More complex sequential building blocks: Storage registers, Shift registers, Counters Available as components in the TTL Catalog
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Chapter #7: Sequential Logic Case StudiesMotivationFlipflops: most primitive "packaged" sequential circuitsMore complex sequential building blocks: Storage registers, Shift registers, Counters Available as components in the TTL CatalogHow to represent and design simple sequential circuits: countersProblems and pitfalls when working with counters:Start-up States Asynchronous vs. Synchronous logicChapter OverviewExamine Real Sequential Logic Circuits Available as ComponentsRegisters for storage and shiftingRandom Access MemoriesCountersCounter Design ProcedureSimple but useful finite state machineState Diagram, State Transition Table, Next State FunctionsExcitation Tables for implementation with alternative flipflop typesSynchronous vs. Asynchronous CountersRipple vs. Synchronous CountersAsynchronous vs. Synchronous Clears and LoadsKinds of Registers and CountersStorage RegisterGroup of storage elements read/written as a unit4-bit register constructed from 4 D FFsShared clock and clear linesSchematic ShapeTTL 74171 Quad D-type FF with Clear(Small numbers represent pin #s on package)Kinds of Registers and CountersInput/Output VariationsSelective Load CapabilityTri-state or Open Collector OutputsTrue and Complementary Outputs74377 Octal D-type FFswith input enable74374 Octal D-type FFswith output enableEN enabled low andlo-to-hi clock transitionto load new data intoregisterOE asserted lowpresents FF state tooutput pins; otherwisehigh impedenceKinds of Registers and CountersRegister FilesTwo dimensional array of flipflopsAddress used as index to a particular wordWord contents read or writtenSeparate Read and Write EnablesSeparate Read and Write AddressData Input, Q OutputsContains 16 D-ffs, organized asfour rows (words) of four elements (bits)Note: no clock! Special care needed!74670 4x4 Register File withTri-state OutputsKinds of Registers and CountersShift RegistersStorage + ability to circulate data among storage elementsShift from left storage element to right neighbor on every hi-to-lo transition on shift signalWrap around from rightmost element to leftmost elementMaster Slave FFs: sample inputs while clock is high; change outputs on falling edgeKinds of Registers and CountersShift Register I/OSerial vs. Parallel InputsSerial vs. Parallel OutputsShift Direction: Left vs. RightSerial Inputs: LSI, RSIParallel Inputs: D, C, B, AParallel Outputs: QD, QC, QB, QAClear SignalPositive Edge Triggered DevicesS1,S0 determine the shift functionS1 = 1, S0 = 1: Load on rising clk edge synchronous loadS1 = 1, S0 = 0: shift left on rising clk edge LSI replaces element DS1 = 0, S0 = 1: shift right on rising clk edge RSI replaces element AS1 = 0, S0 = 0: hold stateMultiplexing logic on input to each FF!74194 4-bit UniversalShift RegisterShifters well suited for serial-to-parallel conversions, such as terminal to computer communicationsKinds of Registers and CountersShift Register Application: Parallel to Serial ConversionParallelInputsParallelOutputsSerialtransmissionKinds of Registers and CountersCountersProceed through a well-defined sequence of states in response to count signal3 Bit Up-counter: 000, 001, 010, 011, 100, 101, 110, 111, 000, ...3 Bit Down-counter: 111, 110, 101, 100, 011, 010, 001, 000, 111, ...Binary vs. BCD vs. Gray Code CountersIn order to avoid circuit hazard!A counter is a "degenerate" finite state machine/sequential circuitwhere the state is the only outputKinds of Registers and CountersJohnson (Mobius) CounterEnd-Around8 possible states, single bit change per state, useful for avoiding glitchesKinds of Registers and CountersA Counter from TTL familySynchronous Load and Clear InputsPositive Edge Triggered FFsParallel Load Data from D, C, B, AP, T Enable Inputs: both must be asserted to enable countingRCO: asserted when counter enters its highest state 1111, used for cascading counters"Ripple Carry Output"74163 Synchronous4-Bit Upcounter74161: similar in function, asynchronous load and resetKinds of Registers and Counters74163 Detailed Timing DiagramCounter Design ProcedureIntroductionThis procedure can be generalized to implement ANY finite state machineCounters are a very simple way to start: no decisions on what state to advance to next current state is the outputExample:3-bit Binary UpcounterDecide to implement withToggle FlipflopsWhat inputs must bepresented to the T FFsto get them to changeto the desired state bit?This is called"Remapping the NextState Function"Counter Design ProcedureExample ContinuedResulting Logic Circuit:K-maps for Toggle Inputs:Timing Diagram:Counter Design ProcedureMore Complex Count SequenceStep 1: Derive the State Transition DiagramCount sequence: 000, 010, 011, 101, 110Step 2: State Transition TableNote the Don't Care conditionsCounter Design ProcedureMore Complex Count SequenceStep 3: K-Maps for Next State FunctionsCounter Design ProcedureMore Complex Count SequenceStep 3: K-Maps for Next State FunctionsCounter Design ProcedureMore Complex Counter SequencingStep 4: Choose Flipflop Type for Implementation Use Excitation Table to Remap Next State FunctionsToggle ExcitationTableRemapped Next StateFunctionsCounter Design ProcedureMore Complex Counter SequencingRemapped K-MapsTC = A C + A C = A xor CTB = A + B + CTA = A B C + B CCounter Design ProcedureMore Complex Counter SequencingResulting Logic:5 Gates10 Literals + Flipflop connectionsTiming Waveform:Self-Starting CountersStart-Up StatesAt power-up, counter may be in any possible stateDesigner must guarantee that it (eventually) enters a valid stateEspecially a problem for counters that validly use a subset of statesSelf-Starting Solution:Design counter so that even the invalid states eventually transition to valid stateImplementationin PreviousSlide!Two Self-Starting State Transition Diagrams for the Example CounterSelf-Starting CountersDeriving State Transition Table from Don't Care AssignmentImplementation with Different Kinds of FFsR-S FlipflopsContinuing with the 000, 010, 011, 101, 110, 000, ... counter exampleRS Excitation TableRemapped Next State FunctionsImplementation with Different Kinds of FFsRS FFs ContinuedCBCB1111A000110A0001100011RC =SC =RB = SB = RA = SA =RCSCCBCB1111A000110A0001100011RBSBCBCB1111A000110A0001100011RASAImplementation with Different Kinds of FFsRS FFs ContinuedRC = ASC = ARB = A B + B CSB = BRA = CSA = B CImplementation With Different Kinds of FFsRS FFs ContinuedResulting Logic Level Implementation: 3 Gates, 9 Literals + Flipflop connections using RB = B (A + C)Could be 4 Gates, 10 Literals + FF connectionsImplementation with Different FF TypesJ-K FFsJ-K Excitation TableRemapped Next State FunctionsImplementation with Different FF TypesJ-K FFs ContinuedCBCB1111A000110A0001100011JC =KC =JB =KB =JA =KA = JCKCCBCB1111A000110A0001100011JBKBCBCB1111A000110A0001100011JAKAImplementation with Different FF TypesJ-K FFs ContinuedJC = AKC = AJB = 1KB = A + CJA = B CKA = CImplementation with Different FF TypesJ-K FFs ContinuedResulting Logic Level Implementation: 2 Gates, 7 Literals + Flipflop ConnectionsImplementation with Different FF TypesD FFsSimplest Design Procedure: No remapping needed!DC = ADB = A C + BDA = B CResulting Logic Level Implementation: 3 Gates, 6 Literals + Flipflop connectionsImplementation with Different FF TypesComparisonT FFs well suited for straightforward binary counters But yielded worst gate and literal count for this example!No reason to choose R-S over J-K FFs: it is a proper subset of J-K R-S FFs don't really exist anyway J-K FFs yielded lowest gate count Tend to yield best choice for packaged logic where gate count is keyD FFs yield simplest design procedure Best literal count D storage devices very transistor efficient in VLSI Best choice where area/literal count is the keyAsynchronous vs. Synchronous CountersRipple CountersDeceptively attractive alternative to synchronous design styleCount signal ripples from left to rightState transitions are not sharp!Can lead to "spiked outputs" from combinational logic decoding the counter's state  No use practically!Asynchronous vs. Synchronous CountersCascaded Synchronous Counters with Ripple Carry OutputsFirst stage RCOenables second stagefor countingRCO assertedsoon after stageenters state 1111also a functionof the T EnableDownstream stageslag in their 1111 to0000 transitionsAffects Count periodand decoding logic Asynchronous vs. Synchronous CountersThe Power of Synchronous Clear and LoadStarting Offset Counters: e.g., 0110, 0111, 1000, 1001, 1010, 1011, 1100, 1101, 1111, 0110, ...D C B AR Q Q Q Q 1 C DCBAL 6 C OO C 3L A L KPTD C B ADR01++LoadUse RCO signal to trigger Load of a new stateSince 74163 Load is synchronous, state changes only on the next rising clock edge0110is the stateto be loadedCLRBADCQ Q Q Q R 1 D C B AL C 6 C O C O3L A L KPTD C B ADR1 0Asynchronous vs. Synchronous CountersOffset Counters ContinuedEnding Offset Counter: e.g., 0000, 0001, 0010, ..., 1100, 1101, 0000Clear signal takes effect on the rising count edgeDecode state todetermine when toreset to 0000Replace '163 with '161, Counter with Async ClearClear takes effect immediately!Random Access MemoriesStatic RAMTransistor efficient methods for implementing storage elementsSmall RAM: 256 words by 4-bitLarge RAM: 4 million words by 1-bitWe will discuss a 1024 x 4 organizationWords = RowsStatic RAM CellStatic RAM CellStatic RAM CellColumns = Bits (Double Rail Encoded)Random Access MemoriesStatic RAM OrganizationChip Select Line (active lo)Write Enable Line (active lo)10 Address Lines4 Bidirectional Data LinesRandom Access MemoriesRAM OrganizationLong thin layouts are not the best organization for a RAM64 x 64SquareArraySome Addrbits selectrow64Select1 of 641616161616Some Addrbits selectwithin rowAmplifers &Mux/DemuxSelect1 of 16D0D1D2D3Random Access MemoriesRAM TimingSimplified Read TimingSimplified Write TimingRandom Access MemoriesDynamic RAMs1 Transistor (+ capacitor) memory elementRead: Assert Word Line, Sense Bit LineWrite: Drive Bit Line, Assert Word LineDestructive Read-OutNeed for Refresh Cycles: storage decay in msInternal circuits read word and write backRandom Access Memories4096x1-bit DRAM OrganizationTwo new signals: RAS, CAS Row Address Strobe Column Address Strobereplace Chip Select & reduces address linesShould be 5(Fig. 7.52)Random Access MemoryRAS, CAS AddressingTo read 1 bit, an entire 64-bit row is read!Separate addressing into two cycles: Row Address, Column Address Saves on package pins, speeds RAM access for sequential bits!Read CycleRead RowRow Address LatchedRead Bit Within RowColumn Address LatchedHigh impedanceOutputsMemory values restoredRandom Access MemoryWrite Cycle Timing(1) Latch Row Address Read Row(2) WE low(3) CAS low: replace data bit(4) RAS high: write back the modified row(5) CAS high to complete the memory cycleRandom Access MemoryRAM RefreshRefresh Frequency:4096 word RAM -- refresh each word once every 4 msAssume 120ns memory access cycleThis is one refresh cycle every 976 ns (1 in 8 DRAM accesses)!But RAM is really organized into 64 rowsThis is one refresh cycle every 62.5 m sec(1 in 500 DRAM accesses)Large capacity DRAMs have 256 rows, refresh once every 16 msecRAS-only Refresh (RAS cycling, no CAS cycling) External controller remembers last refreshed rowSome memory chips maintain refresh row pointer CAS before RAS refresh: if CAS goes low before RAS, then refreshRandom Access MemoryDRAM VariationsPage Mode DRAM:read/write bit within last accessed row without RAS cycleRAS, CAS, CAS, . . ., CAS, RAS, CAS, ...New column address for each CAS cycleStatic Column DRAM:like page mode, except address bit changes signal new cyclesrather than CAS cyclingon writes, deselect chip or CAS while address lines are changingNibble Mode DRAM:like page mode, except that CAS cycling implies next columnaddress in sequence -- no need to specify column address afterfirst CASWorks for 4 bits at a time (hence "nibble")RAS, CAS, CAS, CAS, CAS, RAS, CAS, CAS, CAS, CAS, . . .Chapter SummaryThe Variety of Sequential Circuit Packages Registers, Shifters, Counters, RAMsCounters as Simple Finite State MachinesCounter Design Procedure 1. Derive State Diagram 2. Derive State Transition Table 3. Determine Next State Functions 4. Remap Next State Functions for Target FF Types Using Excitation Tables; Implement LogicDifferent FF Types in Counters J-K best for reducing gate count in packaged logic D is easiest design plus best for reducing wiring and area in VLSIAsynchronous vs. Synchronous Counters Avoid Ripple Counters! State transitions are not sharp Offset counters: easy to design with synchronous load and clear Never use counters with asynchronous clear for this kind of applicationRAM Static RAM Dynamic RAM
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