DESIGN Of LOW-POWER AND HIGH PERFORMANCE RADIX-4 MULTIPLIER.doc

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  DESIGN OF LOW-POWER AND HIGH PERFORMANCE RADIX-4 MULTIPLIER  AIM: The main aim of the project is to design and implement “DESIGN OF LOW-POWER AND HIGH PERFORMANCE RADIX-4 MULTIPLIER”. ABSTRACT: A One-bit adder is designed using modified complementary pass transistor logic (MCPL) The proposed adder is implemented in ! ! bit high radi multiplier to achie#e high speed$ lo% area and less po%er dissipation This circuit is simulated by using &'C schematic design tool and layout is ta*en by Micro%ind  +L', layout CA& tool$ and the analysis is done by using the ',M! analy.er The ! ! bit high radi multiplier is then compared %ith Carry 'a#e Array multiplier (C'A multiplier)$ augh-/ooley multiplier$ and high radi multiplier to sho% the better performance in terms of po%er$ area and delay Propos! #$o!: ,n this paper %e can increase the bit si.e and further %e can compare %ith ut multiplier ,n terms of po%er $ delay and area V.Mallikarjuna (Project manager) Mobile No: +91-8297578555 . ISO: 9001- 2008 CERTIFIED   COMPANY    Branch!: #$ra%a$ & Na'()r  BLOC% DIAGRAM: 0ig1 2adi -! Multiplier TOOLS: 3ilin 4,'5$ Modelsim 6!c APPLICATION AD&ANTAGES:  The proposed 2adi - ! Multiplier may be used in &'P applications because it gi#es better performance in terms of po%er$ delay and P&P V.Mallikarjuna (Project manager) Mobile No: +91-8297578555 . ISO: 9001- 2008 CERTIFIED   COMPANY    Branch!: #$ra%a$ & Na'()r   The proposed adder based multiplier can be used in high speed application  because of its less po%er dissipation and delay REFERENCES: ã 5 Costa$ ' ambi$ and 7ose Monteiro 8A 9e% Architecture fur signed 2adi -Am Pure array Multipliers8 Proceedings of the :: ,555 ,nternational Conference on Computer &esign1 +L', in Computers and Processors (,CC&:) ã  Par*$ M 'hin$ , C Par*$ and C M ;yung$ 82adi -! multiplier %ith regular layout structure$8 5lectronics letter$ #ol<!$ no =>$ pp=!!6-? ã @ ; @amana*a$ T 9ishidha$ T 'aito$ M 'himohigashi$ and ; 'himi.u$ A itachi Ltd$ To*yo 8 A <-ns CMO' =6 =6-b multiplier using complementary pass-transistor logic$8 ,555 7ournal of 'olid-'tate Circuits$ #o=>$ no $pp<-4> ã 2 Bimmermann and / 0ichtner$ 0ello%$ ,555Lo%-Po%er8 Logic 'tyles1 CMO' +ersus Pass-Transistor Logic$8 ,555 7ournal Of 'olid-'tate Circuits$ #ol <$ no ?$ pp=:?4- 4: ã & Mar*o#ic$  9i*olic$ and +  O*lobd.ija$ 8A general method in synthesis of pass-transistor circuits$8 Microelectr 7$ #ol <=$pp 44=- V.Mallikarjuna (Project manager) Mobile No: +91-8297578555 . ISO: 9001- 2008 CERTIFIED   COMPANY    Branch!: #$ra%a$ & Na'()r
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